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Hungry4info
MEX Observations Temporarily Suspended
http://www.spaceref.com/news/viewsr.rss.html?pid=38935
stevesliva
Mars Express steadily returns to routine operation
http://www.esa.int/SPECIALS/Operations/SEMYN9ZW5VG_0.html

Sounds like they expect the wonky flash to be permanently wonky.
stevesliva
More:
http://webservices.esa.int/blog/post/7/1375

Interesting.
stevesliva
Sounds like MARSIS was prime, and working again first:
http://sci.esa.int/science-e/www/object/in...fobjectid=49771

QUOTE
The Mars Advanced Radar for Subsurface and Ionosphere Sounding (MARSIS) instrument on board Mars Express has recently completed a subsurface sounding campaign over the planet's North Pole. The campaign was interrupted by the suspension of science observations several times between August and October due to safe modes and to anomalies in the operation of the spacecraft's Solid-State Mass Memory (SSMM) system. As MARSIS best observes in the dark, which for the North Pole only occurs every few years, it was among the first instruments to resume observations once a partial work-around for the problems had been implemented.
cndwrld
MEX back to full science operations now. After a lot of work.


http://sci.esa.int/science-e/www/object/in...fobjectid=50026
machi
I have always admiration for this kind of repairing something millions of kilometers away.

And this sounds as another good news for us:

"Work is also in hand to resume operation of the Visual Monitoring Camera (VMC – the 'Mars webcam')."
stevesliva
QUOTE (cndwrld @ Feb 15 2012, 05:39 AM) *


This is a great writeup, btw. Came here to link to it!

I'm still curious what causes the SSMM errors, though. A comment here:
http://www.spaceflightnow.com/news/n1202/15marsexpress/
... suggests that the memory system is having bit errors.

Though in the way ESA describes it-- "errors during the transfer of data from the MTL(in the SSMM) to the command cache"-- I wonder if the errors occur not in the memory, but somewhere in a bus between the SSMM and the command cache in the CPU. They also suggest the redundant memory controller didn't do any better.

Page 127 here has a memory system diagram for VEX, pretty much like MEX:
http://dedead.free.fr/projet/01-%20VEX.T.A...CN.00349-02.pdf

That doesn't really help show which bus could be the culprit, though, because they're basically all redundant. I suppose it could be multi-bit-errors in the flash percolating all the way through either memory controller. Except the system should catch those. So I can talk in circles and not know what's really going wrong here. And I'm curious. Anyone know of any other sources?
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